// (C) 2022 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other 
// software and tools, and its AMPP partner logic functions, and any output 
// files from any of the foregoing (including device programming or simulation 
// files), and any associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License Subscription 
// Agreement, Intel FPGA IP License Agreement, or other applicable 
// license agreement, including, without limitation, that your use is for the 
// sole purpose of programming logic devices manufactured by Intel and sold by 
// Intel or its authorized distributors.  Please refer to the applicable 
// agreement for further details.

`define DEBUG_GLOBAL_MAX_ADDR           8           // Debug Global CSR

/*************************************************************************************************************
 * CSR Address Offset                                                                                        *
 *************************************************************************************************************/
`define DEBUG_FPGA_VERSION_ADDR         16'h00
`define DEBUG_REV_CTRL_ADDR             16'h04
`define DEBUG_BUILD_TIME_ADDR           16'h08
`define DEBUG_BUILD_CATEGORY_ADDR       16'h0C
`define DEBUG_DEVICE_LOCATION_ADDR      16'h10
`define DEBUG_SCRATCH_ADDR              16'h14
`define DEBUG_HP_SLOT_LED_ADDR          16'h18
`define DEBUG_POSTCODE_VALUE            16'h1C

/*************************************************************************************************************
 * CSR Default Value                                                                                         *
 *************************************************************************************************************/
`define DEBUG_BUILD_CATEGORY_DEF        01'b0       // Clean Build
`define DEBUG_DEVICE_LOCTAION_DEF       02'b11      // Debug FPGA Location